library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity lab1_tb is
end;

architecture bench of lab1_tb is
   -- define the component
   component lab1
      port( SW    :  IN    std_logic_vector( 9 downto 0 );
            HEX0  :  OUT   std_logic_vector( 6 downto 0 );
            HEX1  :  OUT   std_logic_vector( 6 downto 0 ) );
   end component;
   
   -- define the signals
   signal SW      :           std_logic_vector  (  9  downto   0  );
   signal HEX0    :           std_logic_vector  (  6  downto   0  );
   signal HEX1    :           std_logic_vector  (  6  downto   0  );
     
   -- define a constant time period
   constant PERIOD : time := 5 ns;
   
begin
   -- component instantiation
   DUT   :  lab1 port map (  SW => SW,
                             HEX0 => HEX0,
                             HEX1 => HEX1 );
                                       
   test : process
   begin
      SW <= "0000000000";
      wait for PERIOD;
      SW <= "0001000010";
      wait for PERIOD;
      SW <= "0010000100";
      wait for PERIOD;
      SW <= "0011000110";
      wait for PERIOD;
      SW <= "0000100001";
      wait for PERIOD;
      SW <= "0100101001";
      wait for PERIOD;
      SW <= "1000110001";
      wait for PERIOD;
      SW <= "1100111001";
      wait for PERIOD;
      wait;
      
   end process;
end bench;


